1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a test structure for characterizing integrated circuit etch processes.
2. Description of the Related Art
Fabricating integrated circuits involves placing numerous devices in a single semiconductor substrate and connecting isolated devices though specific electrical paths. Structures that electrically separate or "isolate" one device from another are thus required. Select devices may then be interconnected by conductors extending over a dielectric that isolates those devices. From this perspective, isolation and interconnect routing technologies are two of many critical aspects involved in fabricating a functional integrated circuit.
A popular isolation technology used in integrated circuits involves the technique known as "shallow trench isolation." The shallow trench isolation process is better suited for isolating densely spaced active devices having field regions less than, e.g., 3.0-5.0 .mu.m in the lateral dimension than is the previously developed local oxidation of silicon ("LOCOS") technique. The trench isolation process involves etching a silicon substrate surface to a relatively shallow depth (e.g., between about 0.2 and 0.5 .mu.m) and then filling the shallow trench with a deposited dielectric (referred to henceforth as "trench dielectric"). Some trench isolation processes include an interim step of growing silicon dioxide on trench walls prior to the trench being filled. After the trench is filled, it is then planarized to complete the isolation structure.
In order to connect isolated devices, many integrated circuits purposefully circumvent the isolation structures by routing an interconnect line between devices over the isolation dielectric. This is known as "local interconnect." The interconnect generally connects the source (or drain) region on one device to the source (or drain) region, or to the gate conductor, on another device. Many types of materials may be used to establish local interconnects. For example, local interconnects can be formed from (i) a single or double-doped polycrystalline silicon ("polysilicon"), (ii) a refractory metal silicide upon polysilicon, (iii) multi-layered refractory metal partially converted to silicide, or (iv) refractory metal deposited by physical vapor deposition ("PVD") or chemical vapor deposition ("CVD").
Local interconnects, when covered with a dielectric, allow global interconnects such as metal conductors to extend over the local interconnect and buried contacts. Thus, local interconnects afford an additional interconnect level, provided the added resistance of a local interconnect would not deleteriously affect circuit performance. For this reason, local interconnects are generally used for short interconnect runs relative to much longer metal conductors. Local interconnects are used primarily to interconnect gates and sources and drains in MOS circuits, and are prevalent in, for example, high-density VLSI logic and SRAMs. An SRAM cell layout can be substantially reduced when a local interconnect level and associated buried contacts are used.
FIGS. 1A and 1B depict a partial top plan view and a partial cross-sectional view along line B of FIG. 1A, respectively, of an exemplary integrated circuit topography 10 employing a local interconnect 42. A pair of MOSFET transistors 4 and 6 are arranged a lateral spaced distance apart upon and within a semiconductor substrate. Transistors 4 and 6 include respective conductive gate structures 20 and 30 interposed between respective source/drain regions 16 and 18. The source/drain regions 16 and 18 are arranged within the substrate and are isolated from each other by field isolation regions 14. Local interconnect 42 extends across the substrate and isolation regions from conductive gate structure 20 of transistor 4 to one source/drain region 18 of transistor 6. The local interconnect 42 is oriented such that it does not pass over source/drain regions 16 and cause unwanted shorting between conductive gate structure 20 and source/drain regions 16. Using a local interconnect to couple a gate of one transistor to a source/drain region of another transistor is prevalent in, for example, high density VLSI logic and SRAMs.
Conductive gate structures 20/30 include gate conductors 24/34 residing a spaced distance above substrate 12. As shown in FIG. 1B, gate conductor 34 is spaced above substrate 12 by gate dielectric 32. Spacers 26/36 are formed adjacent opposed sidewalls of gate conductors 24/34 and above lightly doped drain areas such as areas 18a. Metal silicides 28/38 are formed upon upper surfaces of the gate conductors and the source/drain areas (e.g., areas 18b). The gate conductors typically include polycrystalline silicon that is rendered conductive by implanting dopants therein. The gate conductors are formed by depositing polysilicon upon a substrate, followed by etching away select portions of the polysilicon to define the gate conductors.
In contrast, local interconnects can be formed using the so-called damascene process. That is, an interlevel dielectric (such as interlevel dielectric 40) is deposited across the substrate and gate areas, and then trenches are etched through the interlevel dielectric to the underlying gate areas and/or silicided source/drain areas. A conductive material, e.g., tungsten, is deposited into the trenches to a level spaced above the upper surface of the interlevel dielectric. The surface of the conductive material may be removed to a level commensurate with the upper surface of the interlevel dielectric using, e.g., chemical-mechanical polishing. Ohmic contacts (not shown) may also be formed by etching through an interlevel dielectric above the surfaces of interlevel dielectric 40 and local interconnect 42. Openings (i.e., vias) are etched through the interlevel dielectric to underlying structures and then filled with a conductive material. Generally, contacts are used to couple global interconnect to local interconnect, gate conductors, junctions, and other levels of global interconnect.
The trenches in which metal local interconnects are formed may be several thousands of angstroms deep. As such, the time required for etching the trenches may be substantial, particularly if a significant over-etch is included in the process to ensure complete etching of the trenches uniformly across the wafer. The potential thus exists for damage to the underlying substrate and/or isolation regions. In particular, the metal silicide that may be formed upon the active areas to improve electrical connections to the source and drain is typically more resistant to the etchants used to form the trenches than is the silicon dioxide of the isolation regions. As such, because a material discontinuity exists at the interface between the active areas and the isolation regions, such interfaces are particularly subject to attack during the etching processes. If significant etching occurs at such interfaces, local interconnect metal may be introduced into the resulting fissures. Consequently, electrical connection may be made between the heavily doped source/drain regions and the oppositely doped bulk substrate, as well as between the substrate at one transistor and the gate of the other transistor to which the interconnect is coupled, causing the integrated circuit to become grounded or shorted to substrate 12.
FIG. 2A depicts an expanded view of region 2 of FIG. 1B according to an embodiment in which etching at the active region/isolation region interface is minimal. As such, no conductive pathway is formed between the substrate and the transistors formed upon and within the substrate. As shown in FIG. 2A, local interconnect 42 includes a tungsten layer 42b formed upon a titanium underlayer 42a. Titanium layer 42a is formed between tungsten layer 42b and the underlying topography to facilitate adhesion of the tungsten to the silicon dioxide field region and the active region. Alternatively, local interconnect 42 may include a metal exhibiting good adhesion to the underlying topography without the need for an intervening underlayer. As shown in FIG. 2A, the titanium layer is in contact with metal silicide 38 that has been formed upon source/drain regions 18b. Alternatively, the local interconnect may be formed directly upon the source/drain regions in the active areas.
FIG. 2B depicts an expanded view of region 2 of FIG. 1B according to an alternative embodiment in which etching at the active region/isolation region interface is substantial. As such, titanium "spike" 44 is formed in the resultant fissure during deposition of titanium underlayer 42a, such that electrical connection is made between bulk substrate 12 and source/drain region 18b. Unfortunately, however, detection of such destructive over-etching and the resulting electrical connections requires extensive and time-consuming electrical testing that is conducted only after integrated circuit fabrication is completed. The resulting time delay between formation and detection may mean that large numbers of defective integrated circuits are produced before the problem is identified and corrected. Likewise, if visual analysis for defects is performed using, e.g., scanning electron microscopy, the time required to examine sufficient area to detect defects occurring with a low frequency (e.g., on the order of 0.1/cm.sup.2) becomes prohibitive.
It would therefore be beneficial to develop a method for characterizing the etching procedures used in integrated circuit fabrication to test for gap formation between the isolation regions and junction regions of the semiconductor substrate. In particular, it would be advantageous to have the capacity to characterize methods used for etching silicon dioxide layers, such as layers from which interlevel dielectrics are formed. Accurate information on possible over-etching at the active region/isolation region interface would be useful in minimizing or eliminating grounding, shorting, or other etch-related defects in integrated circuits fabricated using the processes being tested.